A fin field-effect transistor (finFET) device includes a fin channel interconnecting a source and a drain. A gate over the fin regulates current flow through the channel. It is oftentimes desirable to employ different channel materials for n-channel finFET (NFET) and p-channel finFET (PFET) devices, such as silicon (Si) and silicon germanium (SiGe), respectively.
Isolation between adjacent devices is typically achieved using shallow trench isolation (STI) whereby an insulator such as an STI oxide is deposited into trenches between the fins. However, forming STI regions with an STI oxide on SiGe fins undesirably results in significant SiGe fin loss due to oxidation during the STI thermal anneal.
To prevent fin loss, a nitride liner can be placed on the fins prior to depositing the STI oxide. With that configuration, however, significant source-drain off state leakage current is experienced in the NFET devices.
It has been found that forming a dipole layer at the fin/STI interface reduces source-drain off state leakage current. See, e.g., U.S. Pat. No. 9,799,654 issued to Ok et al., entitled “FET Trench Dipole Formation” (hereinafter “U.S. Pat. No. 9,799,654”), the contents of which are incorporated by reference as if fully set forth herein. However, implementing the techniques described in U.S. Pat. No. 9,799,654 requires masking steps to enable selective processing of NFET and PFET devices, which increases production complexity, time and overall costs.
Accordingly, improved techniques for reducing off-state current in dual channel CMOS devices via dipole formation and a maskless process would be desirable.